The preferred embodiment of the present invention is directed toward a data receiver in a device such as a double data rate (DDR) synchronous dynamic random access (SDRAM) memory. In a DDR SDRAM, data is sampled at both the rising edge and the falling edge of a clock signal. FIG. 1 shows a known DDR receiver 10.
Double data rate SDRAMs latch data VDQ with both edges of a data strobe DQSin. To be able to do so, a data strobe signal VDQS is received on the SDRAM and then driven to the data receive and latch blocks. In these receive and latch blocks, the data and strobe signals are received in identical receiver elements. The core element of DDR SDRAM receiver elements is usually a differential amplifier 12 (14) or a derivative of a differential amplifier. In the illustrated circuit, the differential amplifier 12 receives the data signal VDQ and the differential amplifier 14 receives the strobe signal VDQS.
Each differential amplifier 12 (or 14) compares the input voltage on the DQ (or DQS) node to a reference voltage VREF to detect the value (HIGH or LOW) of the received signal. At the output of the data receiver 12, the signal DQin is then delayed by delay element 16 to match the delay that is needed for the internal DQS signal to be driven to the data latches 18 and 20 individual receive and latch blocks. Thus the data DQ and the data strobe DQS are realigned at the latches 18 and 20. The delay on the DQS signal results from both the RC delay of the wires and the transition delay of the driver block 22.
After the delay block 16, the data line is split to two latch blocks 18 and 20. In this case, a master-slave flip-flop (MS-FF) 18 retains the data sent with the falling edge of DQS and a master-slave-slave flip-flop (MSS-FF) 20 retains the data sent with the rising edge of DQS. The input stages of both latches 18 and 20 need a sufficient setup and hold time to operate correctly.
FIG. 2 shows a typical differential amplifier 12. (Only amplifier 12 is shown since amplifier 14 includes the same elements.) Differential amplifier 12 includes transistors 26-32 arranged as a current mirror. The differential amplifier 12 typically features some sort of current source 24 as a bias to operate the amplifier. A typical DDR SDRAM includes a number of differential amplifiers and the bias current of all of these devices can add up to several milliamps. This relatively large current consumes a significant portion of the power budget of a DDR SDRAM, especially during standby modes. For specialty DDR SDRAMS, such as a Mobile DDR SDRAM where power consumption is one of the most important features of the device, a more power efficient receiver implementation is desirable.
Other devices use CMOS receivers instead of differential amplifiers. A CMOS receiver is basically an inverter, including an n-channel transistor coupled in series with a p-channel transistor. CMOS inverters, however, have a major drawback as compared to differential amplifiers. The threshold voltage of a CMOS inverter changes greatly over process temperature and voltage (PVT) variations. A changing threshold of a receiver influences the switching point of that receiver. If the threshold of a receiver is “off center,” the duty cycle of the received signal is distorted.
FIG. 3 shows the effects of such a duty cycle distortion through a CMOS receiver. The upper pair of signals (INnomTH, OUTnomTH) display the ideal receiver input to output behavior. The threshold of the receiver (dashed line) is in the middle of the input signal INnomTH. That is, the threshold voltage is substantially equal to the reference voltage. Thus the output signal OUTnomTH has the same duty cycle (i.e., PWin=PWout).
The second pair of signals (INhighTH, OUThighTH) shows the situation where the threshold is higher than the reference voltage. Referring to the figure, the signal INhighTH shows that the receiver has a threshold that is located above the middle of the signal INhighTH. As a result, the signal OUThighTH has a duty cycle that favors the low phase of the pulse (i.e., PWin>PWout).
Finally, the third (lowest on the page) pair of signals (INlowTH, OUTlowTH) shows the situation where the threshold is lower than the reference voltage. When the threshold of the receiver is lower than the middle of the input signal InlowTH, the resulting duty cycle of the output signal OUTlowTH favors the high phase of the pulse (i.e., PWin>PWout).
Those duty cycle distortions severely impact the setup and hold margin of the input stages. Since a DDR SDRAM needs to latch data to both edges of the VDQS, any deviation of the pulse width affects the setup and hold system budget with a factor of two. Large duty cycle distortions are therefore not acceptable, especially at higher speeds where the system budget for setup and hold time gets smaller.